The present invention relates to a ferroelectric memory device having a capacitor element using a ferroelectric material for a capacitor insulating film and to a method for fabricating the same.
An early-stage ferroelectric memory device that was first mass-produced had a small capacity of about 1 Kbits to 64 Kbits and a planar structure in which the lower electrode is larger in size than the upper electrode. In recent years, however, a device having a large capacity of about 256 Kbits to 4 Mbits and a stacked structure in which the lower electrode is smaller than or equal to the upper electrode has been the main target for development. It has been expected to greatly increase the degree of integration and reliability of a nonvolatile memory device by implementing a ferroelectric memory device having the stacked structure.
An example of a conventional ferroelectric memory device having a stacked structure is disclosed in, e.g., Japanese Patent Laid-Open Publication No. 2000-138349.
As shown in FIG. 11A, a capacitor element portion in the conventional ferroelectric memory device is formed above a semiconductor substrate 101 having an impurity diffusion layer 101a formed in an upper portion thereof and having an upper surface covered with an interlayer insulating film 102. A plurality of contact plugs 103 electrically connected to the impurity diffusion layer 101a are formed in the interlayer insulating film 102. A plurality of lower electrodes 104 electrically connected to the contact plugs 103 are buried in a burying insulating film 105 over the interlayer insulating film 102. The lower electrodes 104 are covered with a capacitor-insulating-film forming film 106 composed of a ferroelectric material and with an upper-electrode forming film 107, which are patterned subsequently to be opposed to the lower electrodes 104.
A fabrication method according to the conventional embodiment is characterized in that, to form the capacitor-insulating-film forming film 106 without being affected by the rough configuration of the respective upper surfaces of the interlayer insulating film 102 as an underlying layer and of the lower electrodes 104, the lower electrodes 104 are buried in the burying insulating film 105 by chemical mechanical polishing (CMP) such that the respective upper surfaces of the lower electrodes 104 and the burying insulating film 105 are planarized. This prevents the occurrence of variations in the thickness of the capacitor-insulating-film forming film 106 when it is formed by spin coating if there is a level difference between the upper surfaces of the lower electrodes 104 and the burying insulating film 105 and thereby provides a ferroelectric memory device with high reliability.
However, the conventional ferroelectric memory device has various problems, which will be described below.
The first problem is that, when the burying insulating film 105 deposited to cover the plurality of lower electrodes 104 is polished by CMP, part of the lower electrodes 104 or of a region to be formed with memory cells is left unpolished to form polishing residue since it is difficult to uniformly expose the lower electrodes 104 over the entire surface of the memory cell formation region.
To solve the first problem, over-polishing is performed to further polish the burying insulating film 105. As a result of over-polishing, however, the peripheral portions of the upper surfaces of the lower electrodes 104, which are not the target for polishing, are physically graded off under the pressure exerted during the polishing due to an erosion phenomenon resulting from the different compositions of the adjacent members, i.e., the burying insulating film 105 and the lower electrodes 104. When the peripheral portions of the lower electrodes 104 that have been once planarized are polished together with the burying insulating film 105 in which the lower electrodes 104 are buried, the upper surface of each of the lower electrodes 104 is inclined so that a so-called recess having a level difference d between the center portion and peripheral portion of the upper surface of the lower electrode is formed. This causes the second problem of the rough upper surfaces of the plurality of lower electrodes 104.
If over-polishing is performed with respect to the lower electrodes 104 with roughness observed at the upper surfaces thereof, the third problem arises that the lower electrodes 104 peel off from the burying insulating film 105.
In general, a plurality of memory cells are arranged in rows and columns on a semiconductor substrate. However, since the production yield tends to lower in the peripheral portion of the semiconductor substrate during the fabrication process, dummy electrodes 104a are provided on the outer circumferential portion of the semiconductor substrate. As shown in FIG. 11B, CMP is also used in the fabrication step for the contact plugs 103 in the step preceding the formation of the lower electrodes 104. When the CMP process is performed with respect to the contact plugs 103 and the interlayer insulating film 102, an erosion phenomenon as described above occurs during over-polishing since the members of the contact plugs 103 and the interlayer insulating film 102 have different compositions, so that the thickness of the interlayer insulating film 102 is smaller in a memory-cell main-body region A to be formed with the contact plugs 103. Specifically, the respective heights of the lower electrodes 104 and the dummy electrodes 104a from the semiconductor substrate differ depending on the presence or absence of the contact plugs 103. This leads to the fourth problem that part of the lower electrodes 104 peels off or remains unpolished to form polishing residue when the lower electrodes 104 and the dummy electrodes 104a are planarized. Such peeling off of the lower electrodes 104 from the film or polishing residue causes a bit defect in the ferroelectric memory device. Since the ferroelectric memory devices is a nonvolatile memory device which retains data for a specified period of time and from which the data is read as required, capacitor elements should be formed uniformly for all bits.
As stated previously, variations in the thickness of the interlayer insulating film 102 due to the recess of the lower electrode 104 and the erosion phenomenon of the contact plugs 103 inevitably induce variations in the thickness of the capacitor insulating film 106. As a result, the data retaining abilities of the individual memory cells are no more equal and the reliability of the memory device is thereby reduced.
It is therefore an object of the present invention to provide lower electrodes each having a specified configuration during the formation of capacitor elements each having a capacitor insulating film composed of a ferroelectric material, particularly during the formation of the lower electrodes by CMP, by solving the afore-mentioned conventional problems.
To attain the foregoing object, a ferroelectric memory device according to the present invention is so constructed as to positively utilize the erosion phenomenon which occurs during a CMP process performed in the step of forming the contact plugs or the lower electrodes.
Specifically, a first ferroelectric memory device according to the present invention comprises: a plurality of capacitor elements each formed on a semiconductor substrate and composed of a lower electrode, a capacitor insulating film made of a ferroelectric material formed on the lower electrode, and an upper electrode formed on the capacitor insulating film, each of the lower electrodes being buried in a burying insulating film to have an upper surface planarized relative to an upper surface of the burying insulating film and having a plane configuration such that a distance from an arbitrary position on the upper surface of the lower electrode to a nearest end portion thereof is about 0.6 xcexcm or less.
In the first ferroelectric memory device, each of the lower electrodes has a plane configuration such that the distance from an arbitrary position on the upper surface of the lower electrode to the nearest end portion thereof is about 0.6 xcexcm or less so that the lower electrode is planarized by an erosion phenomenon, which will be described later, without a recess formed in the upper surface thereof. This provides each of the lower electrodes with a specified configuration and prevents the polishing residue of the burying insulating film. This also prevents the peeling off of the lower electrodes from the film and variations in the thickness of the capacitor insulating films so that the data retaining property of each of memory cells is improved.
In the first ferroelectric memory device, a protective film for protecting each of the lower electrodes is preferably formed on a side surface of the lower electrode. In the arrangement, the lower electrodes are less likely to peel off.
In the first ferroelectric memory device, each of the capacitor elements preferably has a contact plug formed under the lower electrode and electrically connected to the lower electrode. The arrangement implements a capacitor element having a stacked structure in which the size of the lower electrode is smaller than or equal to that of the upper electrode.
In this case, a dummy memory cell having a dummy capacitor element including a lower electrode which does not operate electrically is preferably placed in a peripheral portion of a memory cell placement region in which the plurality of capacitor elements are placed and a contact plug connected to the lower electrode of the dummy capacitor element and nearly equal in configuration and material to the contact plug of each of the capacitor elements is preferably formed under the lower electrode of the dummy capacitor element. In the arrangement, the region to be formed with the dummy cell is uniformly reduced in film thickness due to the erosion phenomenon during the formation of the contact plugs by, e.g., CMP, similarly to the memory-cell main-body region. This ensures the planarization of the lower electrodes and the burying insulating film.
In this case, a value of a ratio of a total area of the contact plugs to an area of the memory cell placement region is preferably about 0.3 or less. In the arrangement, the depth of erosion in each of the contact plugs can be reduced to a value which does not affect the performance of the memory device.
In the first ferroelectric memory device, the lower electrode is preferably made of platinum, iridium, ruthenium, an alloy containing at least one of them, or an oxide of iridium or ruthenium. Since the ferroelectric material composing the capacitor insulating film is typically a metal oxide, a material having oxidation resistance such as platinum or iridium or ruthenium having an oxygen barrier property is suitable for the material of the lower electrodes. Besides, an oxide of iridium or ruthenium is also suitable because of its conductivity.
A method for fabricating a ferroelectric memory device according to the present invention comprises: a first step of forming a lower-electrode forming film on a semiconductor substrate and patterning the formed lower-electrode forming film to form a plurality of lower electrodes therefrom, each of the lower electrodes having an outer size such that a recess is not formed by an erosion phenomenon; a second step of depositing a burying insulating film over an entire surface of the semiconductor substrate such that the plurality of lower electrodes are covered with the burying insulating film; a third step of performing polishing with respect to the burying insulating film by chemical mechanical polishing till the lower electrodes are exposed; a fourth step of performing over-polishing with respect to the exposed plurality of lower electrodes and to the burying insulating film to planarize respective upper surfaces of the lower electrodes and of the burying insulating film; a fifth step of forming a capacitor-insulating-film forming film made of a ferroelectric material over the planarized lower electrodes and burying insulating film; a sixth step of forming an upper-electrode forming film on the capacitor-insulating-film forming film; a seventh step of patterning the capacitor-insulating-film forming film to form a plurality of capacitor insulating films therefrom, the capacitor insulating films being opposed to the respective lower electrodes; and an eighth step of patterning the upper-electrode forming film to form a plurality of upper electrodes therefrom, the upper electrodes being opposed to the respective capacitor insulating films.
In the method for fabricating a ferroelectric memory device according to the present invention, each of the plurality of lower electrodes is formed through patterning to have an outer size such that the recess is not formed by the erosion phenomenon and then over-polishing is performed with respect to the exposed lower electrodes and to the burying insulating film, so that the polishing residue of the burying insulating film is not left on the upper surface of each of the lower electrodes. In addition, each of the lower electrodes has an outer configuration such that the recess is not formed by the erosion phenomenon so that the upper surface of the lower electrode is planarized positively.
In the method for fabricating a ferroelectric memory device, the capacitor-insulating-film forming film in the fifth step is preferably formed by spin coating. In the arrangement, the capacitor-insulating-film forming film composed of the ferroelectric material can be coated uniformly on the planarized lower electrodes and burying insulating film.
Preferably, the method for fabricating a ferroelectric memory device further comprises, prior to the first step, the step of: forming, under the respective lower electrodes, a plurality of contact plugs to be connected electrically to the lower electrodes by chemical mechanical polishing, wherein a contact plug placed in a peripheral portion of a memory cell placement region in which the plurality of contact plugs are placed is for a dummy cell which does not operate electrically. In the arrangement, the region to be formed with the dummy cell is uniformly reduced in film thickness due to the erosion phenomenon during the formation of the contact plugs by CMP, similarly to the memory-cell main-body region. This ensures the planarization of the lower electrodes and the burying insulating film.
Preferably, the method for fabricating a ferroelectric memory device further comprises, between the first step and the second step, the step of forming protective films for protecting the lower electrodes on respective side surfaces of the lower electrodes. The arrangement further ensures the prevention of the peeling off of the lower electrodes from the film.
In this case, the protective films are preferably formed by depositing a protective-film forming film over an entire surface of the semiconductor substrate including the lower electrodes and etching-back the deposited protective-film forming film. The arrangement ensures the formation of the protective films on the side surfaces of the lower electrodes.
Alternatively, the protective films are formed preferably from a product generated during the patterning of the lower-electrode forming film. The arrangement obviates the necessity to add an extra step of forming the protective films and reduces the number of fabrication process steps.
Preferably, the method for fabricating a ferroelectric memory device further comprises, between the fourth step and the fifth step, the step of performing etching with respect to respective upper surfaces of the formed lower electrodes by using an etchant for the burying insulating film. In the arrangement, the upper surface of each of the lower electrodes has a depressed (dish-shaped) configuration when viewed in cross section. Even if the residue of the burying insulating film exists in the depressed portion, therefore, it can be removed reliably.
In the method for fabricating a ferroelectric memory device, the lower-electrode forming film in the first step is made of platinum, iridium, ruthenium, an alloy containing at least one of them, or an oxide of iridium or ruthenium.